Advanced-Node Analog / Custom Layout Engineer

Job Summary

We are looking for experienced Advanced-Node Analog / Custom Layout Engineers with hands-on experience in TSMC 3nm technology. The candidate should have strong expertise in custom analog and mixed-signal IC layout, advanced FinFET technologies, and physical verification using Cadence Virtuoso and Calibre tools.

Roles & Responsibilities

• Design and develop full-custom analog, mixed-signal and custom digital layouts for advanced-node semiconductor designs.

• Work on TSMC 3nm technology and support advanced FinFET layout methodologies.

• Perform block-level layout development, floorplanning, placement, routing and full-chip integration.

• Use Cadence Virtuoso Layout Editor (VLE/VXL) for custom layout implementation.

• Perform physical verification using Calibre DRC/LVS and resolve design violations.

• Ensure layout quality through DRC, LVS, DFM, antenna checks and EM/IR verification.

• Apply matching, shielding, guard-ring and parasitic-reduction techniques.

• Coordinate with analog design, physical verification and integration teams.

• Support layout debugging, optimization and timely tapeout deliverables.

Mandatory Requirements

• 4–6 years of experience in Analog / Custom Layout Design.

• Mandatory hands-on TSMC 3nm project experience of at least 3–6 months.

• Strong proficiency in Cadence Virtuoso VLE/VXL.

• Hands-on experience with Siemens / Mentor Calibre DRC/LVS.

• Strong understanding of advanced FinFET technology and custom layout methodologies.

• Experience in DRC, LVS, DFM, antenna checks and physical verification.

• Ability to independently handle block-level layout development and debugging.

• Maximum notice period of 15 days.